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FAN8048
2 DC-DC Converter & 4-CH PWM Motor IC
Features
H-Bridge PWM Driver
* 4 Channels direct PWM H-bridge drivers * Digital input and direct PWM output * Internal power switches - ON state resistance : 2.0 (typ.), which value added the upper and the lower switches
Descripation
The FAN8048 is a monolithic integrated circuit suitable for a 4 channels direct PWM H-bridge driver which incorporates two switch-mode step up-down converter with synchronous rectification provides local microprocessor and servo IC power in portable CD players and portable devices.
Synchronous DC-DC Converter
* * * * Built-in step up converter (VG converter) Built-in two synchronous step up-down converter Built-in short circuit protection Internal Switches - Power Switch : 0.4 (typ.) at 500mA -. Synchronous-Rectifier Switch : 0.4 (typ.) at 500mA 48-LQFP-0707
Others
* * * * * Built-in power-on reset circuit Built-in battery charge circuit Built-in voltage regulator control circuit Built-in thermal shutdown (TSD) circuit Buit-in channel mute circuit
Typical application
* Portable CD-MP3 player
Ordering Information
Device FAN8048 Package 48-LQFP-0707 Operating Temp. -30C ~ +85C
Rev. 1.0.0
(c)2004 Fairchild Semiconductor Corporation
FAN8048
Pin Assignments
LG 48 VG RST OFF ON SPRT SPGND PCT CLK SOFT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 DSW1 20 21 22 23 24 DCIN PGND CH1+ CH147 46 45 CH2+ CH2- PVCC CH3+ 44 43 42 41 CH3- CH4+ 40 39 CH438 PGND 37 36 35 34 33 32 CH4F CH4R CH3F
CH3R CH2F CH2R CH1 MUTE DGND CHGSW CHGCON CHGSEN
FAN8048
31 30 29 28 27 26 25
EA1O EA1EA2O
EA2- VSYS2 USW2 PGND DSW2 VIN
PGND USW1 VSYS1 REG
2
FAN8048
Pin Definitions
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Name VG RST OFF ON SPRT SGND PCT CLK SOFT EA1O EA1EA2O EA2VSYS2 USW2 PGND DSW2 VIN DSW1 PGND USW1 VSYS1 REG DCIN CHGSEN CHGCON CHGSW DGND MUTE CH1 CH2R CH2F CH3R CH3F CH4R CH4F PGND CH4CH4+ CH3CH3+ PVCC CH2CH2+ I/O O I I I O I O I O I O I I I I I I I I I O O O O O O Pin Function Description Gate voltage for power MOSFET drive Power-on reset output System-off signal input System-on signal input Short circuit protection delay time setting capacitor Pre-driver ground Triangular waveform pin Clock input Soft start time setting capacitor of DC-DC converter 1 and 2 Error amplifier output of DC-DC Converter1 Error amplifier inverting input of DC-DC converter1 Error amplifier output of DC-DC converter2 Error amplifier inverting input of DC-DC converter2 Output of DC-DC converter2 DC-DCconvereter2 coil driving pin 1 Power ground DC-DC convereter2 coil driving pin 2 Input voltage of DC-DC coverter 1 and 2 DC-DC convereter1 coil driving pin 2 Power ground DC-DC convereter1 coil driving pin 1 Output of DC-DC converter1 Regulator control output Adaptor power supply input pin Charger current sense Input Charger control output Charger mode switch input Digital circuit ground Channel mute input CH1 input pin CH2 reverse input pin CH2 forward input pin CH3 reverse input pin CH3 forward input pin CH4 reverse input pin CH4 forward input pin Power ground Channel 4 negative output Channel 4 positive output Channel 3 negative output Channel 3 positive output Power supply for H-bridge driver Channel 2 negative output Channel 2 positive output
3
FAN8048
Pin Definitions (Continued)
Pin Number 45 46 47 48 Pin Name CH1CH1+ PGND LG I/O O O Pin Function Description Channel 1 negative output Channel 1 positive output Power ground VG voltage up coil driving pin
4
FAN8048
Internal Block Diagram
LG PGND CH1+ CH1CH2+ CH2PVCC CH3+ CH3CH4+ CH4PGND
48
47
46
45
44
43
42
41
40
39
38
37
PVCC
PVCC
PVCC
H-Bridge 4
H-Bridge 1
H-Bridge 2
H-Bridge 3
PVCC
S3 S4 S1 S4
S1 S2 S3 S2
VG
1
VSYS1 VIN VSYS2
PRE-DRIVER
CH4F
D R V
CH4R 36 35 CH4F CH4R CH3F CH3R CH2F CH2R CH1
CH3R CH3F CH2R
RST
2
0.5V VSYS1
CH2F CH1R
3-State Input Control
34 33 32 31 30
OFF ON SPRT SGND
3 4 5 6 7 SYSTEM Control
SYSTEM OFF SYSTEM ON
CH1F
29
MUTE
PCT
OSC
28
DGND
CLK
8
SOFT
9
Battery Charger Switch
STEP UP/DOWN CONVERTER 2 STEP UP/DOWN CONVERTER 1
27 26 25
CHGSW
CHGCON
EA1O
10 0.9V
Driver & Logic
Driver & Logic
CHGSEN
EA1-
11 0.9V
Regulator & Current Control
EA2O
12
13
EAI2-
14
15
16
17
DSW2
18
VIN
19
20
21
22
23
REG
24
DCIN
VSYS2 USW2 PGND
DSW1 PGND USW1 VSYS1
5
FAN8048
Absolute Maximum Ratings (Ta = 25xC)
Parameter H-bridge driver supply voltage Predriver supply voltage Primary side input voltage of DC-DC converter Output voltage of DC-DC converter1 Output voltage of DC-DC converter2 AC adapter supply voltage H-bridge driver output current Power dissipation Operating temperature Stroage temperature Symbol PVCC VG VIN VSYS1 VSYS2 VDCIN IO PD TOPR TSTG Value 7 12 7 7 7 12 500 1.0 -30 ~ +85 -55 ~ +150 Unit V V V V V V mA W C C
Power Dissipation Curve (Air Condition = 0m/S)
PD[W] 1.75
1.5 1.25 1 0.75 0.5 0.25 0 0 25 50 75 100 125 150
SOA
Ambient Temperature []
Notes: 1. When mounted on 2mm x 114.3mm x 1.6mm PCB (FR-4 glass epoxy material). 2. Refer: EIA/ J SED 51-2 and EIA/ J SED 51-3 JSED51-2 : Integrated circuits thermal test method environmental conditions - Natural convection JSED51-3 : Low effective thermal conductivity test board for leaded surface mount packages 3. Do not exceed PD and SOA(Safe Operating Area).
Recommended Operating Conditions (Ta = 25xC)
Parameter H-bridge driver supply voltage Power supply of DC-DC converter Output voltage of DC-DC converter1 Output voltage of DC-DC converter2 AC adaptor supply voltage Symbol PVCC VIN VSYS1 VSYS2 DCIN Min. 1.2 1.8 2.0 1.6 5.0 Typ. 2.4 2.4 7.0 Max. 4.5 4.5 3.6 VSYS1 10.0 Unit V V V V V
6
FAN8048
Electrical characteristics
(PVCC=VIN=2.4V, VSYS1=VSYS2=2.7V, VG=7.0V, DCIN=0V, CPCT=470pF, Ta=25C,unless otherwise specifid) Parameter CURRENT PVCC quiescent current VIN operating current DCIN operating current VG operating current1 VG operating current2 (Note1) VSYS1 operating current VSYS2 operating current VG CONVERTER PART VG output voltage VG converter start voltage Oscillation frequency VSYS voltage at voltage up mode VSYS Load Stability at voltage up mode VSYS voltage at voltage down mode VSYS load stability at voltage down mode
VSYS output stability at voltage up/down
Symbol IPVCC IVIN IDCIN IVG IVG4CH IVSYS1 IVSYS2 VON = 0V DCIN = 5V
Conditions -
Min. Typ. Max. Unit 1.6 1.0 1.5 3.0 3.0 3.0 1.0 1.5 2.0 5.0 1.0 A mA mA mA mA mA mA
Non driving 4 channels Driving by 4 channels
SYNCHRONOUS DC-DC CONVERTER PART VVG VVGST FLG VUP VUP VDOWN VDOWN VUPDW VEINTH VEOL IEIN IESINK VEI=0.8V IVG=1mA VG=3 5V Sweep VG=3.5V, VLG=5V VIN=2.0V, ISYS=100mA VIN=2.0V, ISYS=0 to 150mA VIN=3.0V, ISYS=100mA VIN=3.0V, ISYS=0 to 150mA VUPDW=VUP-VDOWN 6.0 3.3 65 2.58 -30 2.58 -30 -30 0.86 -1 150 1 7.0 3.9 100 2.7 1.0 2.7 1.0 0 0.9 0.16 0.1 8.0 4.5 135 2.82 30 2.82 30 30 0.94 0.2 1 V V KHz V mV V mV mV V V A A mA
STEP UP/DOWN CONVERTER (COMMON))
ERROR AMPLIFIER Error amplifier threshold voltage Error amplifier output voltage Error amplifier input current Error amplifier source current Error amplifier sink current VSYS1 OPTION CIRCUIT Error amplifier1 short circuit detection voltage SPRT input current1 SPRT input current2 SPRT threshold voltage SOFT input current SPRT/SOFT discharge reset voltage Voltage in switching between the starter and normal modes Vstn hysterisis voltage (Note1) Veos Isprt1 Isprt2 Vsprth Isoft Vdis Vstn Vsthys SPRT=L H VEI=0V, VSPRT=0V OFF=VSPRT=0V VPCT=0.3V, VEO=0.4V,VEI=0V, DSW=H L VSOFT=0V VSYS1=1.3 1.7V VSPRT, VSOFT=L H VSYS1=1.5 2.0 V,DSW=H L VSYS1=1.5 2.0 V 1.20 -9 -16 0.4 -13 1.30 1.70 100 1.35 -6 -12 0.5 -10 1.48 1.84 200 1.45 -4 -8 0.6 -7 1.62 1.95 300 V A A V A V V mV
IESOURCE VEO=0V, VEI=0V
7
FAN8048
Electrical characteristics (Continued)
(PVCC=VIN=2.4V, VSYS1=VSYS2=2.7V, VG=7.0V, DCIN=0V, CPCT=470pF, Ta=25C,unless otherwise specifid) Parameter VSYS2 OPTION CIRCUIT VSYS2 voltage at buck mode operation Load stability of VSYS2 at buck mode operation OSCILLATOR (PCT) Source current Sink current Oscillation frequency1 Oscillation frequency2 Maximum duty ratio (Note1) OUTPUT SWITCHES On resistance of upper switch On resistance of lower switch Leakage current of upper switch Leakage current of lower switch POWER-ON RESET RST threshold voltage1 Hysteresis voltage1 RST threshold voltage2 Hysteresis voltage2 CONTROL INPUT System-on threshold voltage System-on input low level voltage System-on input current System-off threshold voltage System-off input low level voltage System-off input current H-BRIDGE PWM DRIVER PART (CH1) Out on Resistance Input Resistance High level Input voltage Low level Input voltage Rising Time (Note1) Falling Time (Note1) Minimum Pulse Width (Note1) RON1 RIN1 VIH1 VIL1 TRISE1 TFALL1 TMIN1 Top + bottom switches 2.2 2.0 50 0.2 0.2 300 3.0 0.5 K V V s s ns VONTH VONL ION VOFFTH VOFFL IOFF VSYS1=VSYS2=0V VSYS1=VSYS2=0V VON=0V VSYS11.4
Symbol
Conditions VIN=2.4V, VSYS2=1.8V ISYS2=100mA VIN=2.4V, VSYS2=1.8V ISYS2=0 100mA No CLK, At self oscillation CLK=88.2kHz, At synchronization mode CLK=88.2kHz
Min.
Typ.
Max.
Unit
VBUCK VLS
-30
1.8 0
30
V mV
ISOURCE ISINK FOSC1 FOSC2 DMAX
34 11 45 85.2
42 14 60 88.2 75
50 17 75 91.2
A A KHz KHz %
RONSWU Switch A and D, ISYS=500mA RONSWL ILSWU ILSWL VRST1 VRST1 VRST2 VRST2 Switch B and C, ISYS=500mA Switch A and D Switch B and C VIN=2.4V, VSYS2=1.0 1.8V VIN=2.4V, VSYS2=1.8 1.0V VSYS2=2.7V, VIN=1.0 1.8V VSYS2=2.7V, VIN=1.8 1.0V
1.20 40 1.30 50
0.4 0.4 0 0 1.35 70 1.45 80
VIN 0.65
0.6 0.6 2 2 1.50 100 1.60 110
A A V mV V mV
VIN -1.0
V 26 V A V V -55 A
16
VSYS11.15
6
-70
-85
8
FAN8048
Electrical characteristics (Continued)
(PVCC=VIN=2.4V, VSYS1=VSYS2=2.7V, VG=7.0V, DCIN=0V, CPCT=470pF, Ta=25C,unless otherwise specifid) Parameter (CH2,3,4) Out on Resistance Input Resistance High level Input voltage Low level Input voltage Rising Time (Note1) Falling Time (Note1) Minimum Pulse Width (Note1) CONTROL INPUT Mute input high voltage Mute input low voltage Regulator output voltage Line regulation of regulator Load regulation of regulator CHGON Current Constant Charge Current CHGSW-on high voltage CHGSW-on low voltage THERMAL SHUT DOWN Operating temperature (Note1) Thermal hysteresis (Note1)
Notes: 1. Design reference value
Symbol RON RIN VIH VIL TRISE TFALL TMIN VMUTEH VMUTEL VVIN Vdc Vrl Ichon Ichg VCHGSWH VCHGSWL TSD THYS
Conditions Top + bottom switches DCIN=6.5V, Ivin1=200mA
DCIN=5V 7V, Ivin1=200mA
Min. 2.2 2.2 3.7 -50 -40 15 400 2.0 -
Typ. 2.0 30 0.2 0.2 300 4.0 0 0 450 150 20
Max. 3.0 0.5 0.5 4.3 50 10 500 0.5 -
Unit K V V s s ns V V V mV mV mA mA V V C C
REGULATOR AND CHARGER PART
Ivin1=0 200mA Rs=1.1 -
9
FAN8048
Application Information
1. System Control and Protection Functions 1-1. System Enable/Disable Function
As shown in Figure 1, system enable ON (pin4) should be set low (typically under VIN - 0.65V) only once until OFF (pin3) receives the disable signal (typically under VSYS1 - 0.85V), then all circuits remain in enable status. Also, to prevent malfunction, this function activates when the circuit short condition exists such as over current or circuit shorts, the whole circuit becomes the disable. When the circuit is enabled, to obtain the necessary power (VG) to operate the internal circuits and upper side output power switches of the 4 channels H-bridge driver, the VG converter circuit is activated. Also, to stably operate all circuits, the VG converter keeps other circuits from activating until the output voltage of the VG converter reaches the specific voltage (3.9V). When the output voltage of the VG converter reaches 3.9V, the first DC-DC converter (DC-DC Converter1) activate. And when output voltage of DC-DC converter1(VSYS1) reaches 1.35V, the second converter (DC-DC Converter2) activates in sequence. The circuit activation sequence as stated above and a flow chart are shown in Figure 3 and Figure 4.
1-2. Channel Mute Function
When MUTE (pin29) is high (typically above 2.2V), the mute circuit activates, so the all motor driver (4 channels H-bridge driver) outputs are in mute state; on the other hand, when it is low (under 0.5V), mute state is off.
1-3. Thermal Shut Down(TSD) Function
This thermal shutdown (TSD) function is designed to protect the chip from being damaged as the chip's internal temperature rises. If the TSD circuit activates, all motor driver (4 channel H-bridge drivers) outputs are in mute state. When the chip's internal temperature reaches 150C (typical), then the TSD circuit is activated, and when the chip temperature falls to 130C or below, the TSD circuit is deactivated and the output drivers operate normally.
Mute Circuit
MUTE 29
Channel Mute
125
150
TSD Short Circuit Detector
VSYS1
6uA
12uA
EA1O 10
1.35V
OFF SPRT CSPRT
3 5 System_OFF
0.5V
VSYS1 22 ON VG
4 1 R1
DC-DC Converter Wake-up Singnal
Start_up Circuit
VSYS1<1.65V
System_ON
Bias & Refernece
Bias
System_ON
R2
Vref1
DC-DC Converter
VG Converter
Figure 1. Block Diagram of System Control Circuit
10
FAN8048
1-4. Power-On Reset (POR) Function
FAN8048 has two DC-DC converters to supply stable power to external circuits and components of the CD player set. Therefore, for these output voltages of DC-DC converters to provide stable power to external circuits and their components, the DC input voltage,VIN, and the output voltages of converter, VSYS1 and VSYS2, monitoring function is required. The DC input voltage, VIN, and the output voltage of converter2 are individually divided by the internal resistors and then compared with the internal 0.5V reference voltage, VREF2, to determine the low voltages condition. This power on reset (POR) circuit is shown in Figure2.
VSYS2 VIN
14
VSYS1
18
2
RST
Vref2
RST
VSYS1
22
Figure 2. Block Diagram of Power On Reset
1-5. Power Sequence
The following graph and flowchart of Figure 3 and Figure 4 show the power sequence of the VG converter and two DC-DC converters (DC-DC converter1 and DC-DC Converter2); herein, VG converter generates power for internal circuits and upper side output power switches of the 4 channels H-bridge driver, and the DC-DC converters supply the external circuits and components.
Voltage VG=7.0V
3.9V VSYS1 VRST VSYS2 1.35V
Hysteresis
t
Converter 1 Converter 2 Wake-up Wake-up Reset Signal
Figure 3. Plot of Power Sequence
11
FAN8048
Start
SYSON
SYSOFF
VG Converter Wake-up
Yes No
VG > 3.9V
Yes
DC-DC Converter 1 Wake-up
Yes No
VSYS1 > 1.35V
Yes
DC-DC Converter 2 Wake-up
Start-up Mode
Yes No
VSYS2 > 1.35V
Yes Yes
VSYS1 > 1.84V
No
SYSON = LOW
No
Yes
EA1O < 1.35V Time < Tsprt
No
Yes
SYSTEM READY
Normal Mode
SYSTEM OFF
Figure 4. Flow Chart of Power Sequence
12
FAN8048
2. H-Bridge Driver (CH1, CH2, CH3 and CH4 )
2-1. H-Bridge Driver for Actuators and Sled Motor (CH2, CH3 and CH4)
Channel 2, channel 3, and channel 4 have two inputs FWD and RVE and an H-bridge type of output to the forward or reverse Sled motor and the Focus and Tracking actuator as shown in Figure 5. The H-bridge driver operation is as in the following logical truth table below. That is, to forward or reverse, the output is the same as the input, and when the two input signals match, the lower switching devices (switches B and C) are turned-on, Sled motor, Focus and Tracking actuator are in braking state.
PVCC VG VSYS
A
VA
D
OUT+
REV
Predriver
FWD
32 31
VB VC
44
43
VD
OUT-
LOGIC AND PREDRIVER
B
C
Figure 5. Block Diagram of H-Bridge driver for CH2, CH3 and CH4
2-2. Logical Truth Table
FWD L L H H REV L H L H OUT+ L L H L OUTL H L L Function Brake Reverse Forward Brake
2-3. H-Bridge driver for spindle motor (CH1)
Figure 6 shows spindle motor driver. The circuit consists of 3-states of input (High, Low, and High impedance) to perform forwarding, reversing, and braking of the motor. The detailed operation is shown in logical truth table.
VSYS1
PVCC VG
MO1
50K
70K
40K
A
VA
D
CH1+
46
VSYS
CH1 30
MO2 50K 60K 80K
Predriver
VB VC VD
45
CH1-
B
C
LOGIC AND PREDRIVER
OUTPUT STAGE
Figure 6. Block Diagram of H-Bridge driver for Spindle motor
2-4. Logical Truth Table
INPUT H L Z
Note: 1. Z is high impedance input
MO1 H L L
MO2 H L H
CH+ H L L
CHL H L
Function Forward Reverse Brake
13
FAN8048
3. DC-DC Converter (VG Converter and Synchronous DC-DC Converter)
3-1. VG Converter (Step up Converter)
The VG converter is used to generate necessary power (VG) for upper side output power switches operation of 4 channels Hbridge driver and other internal circuit operations as shown in Figure 7. The output voltage (VG) of VG converter is internally set to 7.0V, and it activates DC-DC Converter 1 when VG converter output voltage reaches 3.9 V. Also VG converter has an oscillator function, which is required for switching operations and to minimize external components.
LG
48
D1
LG
DC-DC Converter Wake-up Singnal
1
Vref1
VG
VBAT
SW
R1
CG
R2
Sawtooth
SYSTEM_ON
FAN8048
Clock
4
ON
Figure 7. Set up Converter (VG Converter)
3-2. Synchronous Step-up/Down Converter
The FAN8048 provides high efficiency and low noise power for applications such as portable instrumentation. Figure 8 shows the functional block diagram of synchronous step up/down converter.
DSW
19 18 21
USW
22
Start Comp
1.79V
VSYS
SPRT 5
VA
Stop Comp
VD
0.5V 1.27V
Logic & predriver
VBAT
VB VC
VCOM
VA VB VC VD
Start & Short Circuit Protection VZ1 VX
CP
Error Amp
10
RC CC
R1
11
VZ2 VY
0.56V 0.9V
Power Stage
R2
PCT
7
PCT OSC2
OSC2 PCT
9
VSYS
1.48V
SOFT
VCOM
CLK
8
Sync. Clock
FAN8048 DC-DC Converter
Figure 8. Block diagram of Step-up/down converter
In Figure 8, the output voltage (VSYS) of DC-DC converter is calculated as follows:
VSYS = VREF x (1 + where, VREF
R1 ) [V ] R2 = 0.9[V ]
14
FAN8048
3-3. Oscillator
Oscillator frequency is determined by the charging/discharging current iCG and iDCG of the internal circuit and capacitor (CPCT) connected to PCT (pin7) and ground. To change oscillator frequency, you may change the CPCT capacitor. For example, the external capacitor (CPCT) value can be calculated as follows:
t PCT = f PCT =
C PCT x VPCT C PCT x VPCT C PCT x VPCT (iCHG + iDCG ) + = iCG iDCG iCG x iDCG 1 t PCT = iCG x iDCG C PCT x VPCT x (iCG + iDCG )
C PCT =
iCG x iDCG f PCT x VPCT x (iCG + iDCG )
Where, iCG is charging current, which is 42uA, iDCG is discharging current, which is 14uA, and oscillator peak-peak voltage, VPCT is approximately 300mV. This oscillator is designed to synchronize the frequency of the oscillator itself to the clock pulse frequency separately input to external CLK (pin8). To utilize this function, the oscillator frequency itself should be configured lower than the frequency of the external synchronous signal.
3-4. Error Amplifier
The error amplifier of the DC-DC converter is used to amplify the difference between internal reference voltage and output voltage. This amplified voltage generates a square wave pulse corresponding to the difference of triangular waveform-PCT output formed by triangular wave oscillatory circuit of pulse width modulation comparator (PWM comparator), whereby the square wave pulse stabilizes the output voltage by operating the DC-DC converter's switching devices through the operation circuit. The most well-known system stabilization method using an error amplifier is pole-zero compensation. Detailed system design standards and methods will be discussed in a later section of this document.
3-5. Short Circuit Protection Function
The short circuit protection is a function to protect circuits from being damaged from various abnormal conditions such as over current or circuit shorts; and on this occasion, when the error amplifier output voltage, EIO1, (pin10) of DC-DC converter1 reaches the specific voltage (typically 1.35V), the internal current source, iSPRT, start charging the external capacitor, CSPRT connected between SPRT(pin5) and ground as shown in Figure 1 and the DC-DC converter circuit will be shutdown. Also, to prevent malfunction, this function activates only when the circuit short condition exists for a certain amount of time. This time setting (TSPRT) is determined according to the capacitance of external capacitor CSPRT, and its formula is as follows:
TSPRT =
Where, iSPRT is charging current, which is 6uA.
CSPRT x 0.5 [sec] iSPRT
3-6. Soft Start
This function limits overshoot in the initial operation. This circuit operates when DC-DC converter 1 output voltage rises over a specific voltage (typically 1.48V), thereafter it starts charging the external capacitor CSOFT connected between SOFT (pin9) and Ground. It restricts the error amplifier output voltage caused by sharp-rising capacitor voltage. Soft start time is determined by the following formula: When the output voltage of the conveter, VSYS1, is brought above typically 1.48V, the soft start function is enable and the internal current source is begin to charging the capacitor, CSOFT. A detailed diagram of this fuction is shown in Figure 8. The component CSOFT provide a slow ramping voltage on the SOFT pin to provide a soft start function. The time constant in this case is shown by the next formular.
TSOFT = CSOFT x iSOFT = CSOFT x10uA[sec]
where, iSOFT = 10uA
15
FAN8048
3-7. Operation mode of Step-up/down converter
Figure 9 shows the connection of the four internal output power switches, external Inductor, and input/output voltage, which are components of the FAN8048 built-in DC-DC converter. As shown in Figure 10, the DC-DC converter determines a switching operation mode (Buck, Buck-Boost and Boost) according to the relationship between control voltage VX and VY and oscillator output voltage VPCT. Also, the DC-DC converter indicates the different operational statuses of output power switch (Output switches, A, B, C, and D) according to operational mode. Herein, control voltage VX is the output voltage of error amplifier, and voltage VY is level shift voltage in VX.
VIN DSW
18 19 21
USW VSYS
22
A
VA
D
VD
VB
VC
B
C
Figure 9. Simplified Diagram of Output Swiches
75%
DMAX_BOOST Switch A ON B OFF PWM CD Swiches DMIN_BOOST Four Switches PWM DMAX_BUCK Switch D ON C OFF PWM AB Swiches
0%
Boost Mode
VX > VPCT VX > VY VX VPCT VY VPCT VY > VPCT
Buck/Boost Mode
Buck Mode
VY > VX
Duty
Figure 10. Switching control vs. internal control voltages, VX and VY
16
FAN8048
3-8. Buck(Step-down) converter mode (VIN > VSYS)
The step-down converter keeps the average output voltage VSYS lower than DC input voltage VIN all the time. Figure 11-a shows a conceptual circuit diagram of the step-down converter in case an electrical load is pure resistance. Herein, all switching devices are supposed to be at ideal conditions and instantaneous output voltage VSYS is dependent on the status of switching devices. That is, the input/output of the step-down converter is obtained by the following formula according to the Volt-Sec balance condition and each waveform is shown in Figure.11-b, where D means duty cycle. In this formula, since duty ratio D is smaller than 1.0, average output voltage VSYS is always displayed in the lower range of the DC input voltage.
VSYS =
where, D is duty cycle.
1 x VIN [V ] D
D=
TON TS
In practical application circuits, there are several drawbacks as follows: (1) As most practical circuits are not exposed to pure electrical resistance loads, but to inductive loads and because of the stray inductive there is the switch would have dissipate the inductive energy and therefore it may be destroyed. . (2) This is not the case of most application circuit, but when output voltage fluctuates between zero and power voltage VIN, a low pass filter composed of an inductor and capacitor is required to minimize the output voltage ripple. Figure 12 shows the operation waveform of internal control voltage VX and VY and output power switching devices in Stepdown converter mode. When the internal control voltage VY is higher than control voltage VX and triangular waveform VPCT, switch D is always turned-on and switch C is always turned-off in step-down converter mode. The switching operation of switch A is activated by the signal generated by comparison between internal control VX and triangular waveform voltage VPCT. Also, synchronous switch B remains turned-on during synchronous switch B turn-off time. That is, in step-down converter mode, switch A and B always activate in opposite switching operations. The peak-peak ripple voltage (VSYS) of output voltage is calculated using the following formula:
VSYS =
1 1 I L TS TS VSYS Q x= x (1 - D)TS = xx 2 8C CO CO 2 2 L
I L = VSYS (1 - D)TS L
Where, IL is the inductor current from Figure11 (b) during turn-off (tOFF).
The value of the output capacitor to reduce output voltage ripple is calculated using the following formula.
C=
TS VSYS 2 x (1 - D)TS 8L VSYS
The average value of the inductor current at boundary between continuos and discontinuous conduction mode is
1 DTS I LB = iL , peak = (VIN - VSYS ) 2 2L
where,
VIN =
VSYS [V ] D
So to obtain the inductor value using the above formula, the redefined formula is as follows:
L=
VSYS (1 - D)TS 2 I O ,min
17
FAN8048
A
D
VA
VIN
VB
B
VC
C
VSYS
R
(a)
VL
0
A
(VIN-VSYS)
VSYS
t
B
(-VIN)
iL=IO
0
Ton
Toff
t
Ts
(b)
Figure 11. Synchronous Step-down Converter
VY PCT VX
VA
VB
VC
Low High
VD
Figure 12. Switches operation waveforms during Buck Converter mode
18
FAN8048
3-9. Buck-Boost (Step-down/up) Converter Mode (VIN = VSYS)
As shown in Figure.13-a, the synchronous buck-boost converters take the mixed form of step-up and step-down converters. That is, in case switching devices in the series connection of the two converters activate in the same duty ratio, the input/output relationship during normal conditions can be expressed as follows: Namely, the output voltage VSYS can be higher or lower than DC input voltage VIN according to duty ratio D.
VSYS =
D VIN [V ] 1- D
As shown in Figure 13-b, the current flowing through the inductor is constant in continuous conduction mode. And the input and output voltages relationship formula can be defined as follows, because , the integral of the inductor voltage over one time period to zero.
V SYS DT S + ( -V SYS )(1 - D )TS = 0 V SYS D = V IN 1- D
Assuming a lossless circuit, input and output power are the same (Pin=Po) and the above formula can be redefined as follows:
I SYS 1 - D = I IN D
As you can see in Figure 14, when internal control voltage VX and VY remain in the triangular waveform voltage VPCT range, the converter acts as a step-up or step-down converter mode according to DC input voltage VIN and electrical load VSYS and ISYS status. As displayed in Figure13-a, in this operation mode all four switching devices of the output terminal activate upon operational mode step-up or step-down. Figure13-b shows the operational waveform of each section in this activation mode.
19
FAN8048
A
D
VA
VIN
VD
B
VB
VC
VSYS C
R
(a)
VL
0
A
(VIN)
VSYS
t
B
(-VSYS)
iL=IIN
0
Ton
Toff
t
Ts
(b)
Figure 13. Synchronous Step-up/down Converter
PCT VY VX
VA
VB
VC
VD
Figure 14. Output switches operation and waveforms at Buck/Boost (Step-up/down) mode
20
FAN8048
3-10. Boost (Step-up) converter mode (VIN < VSYS)
The step-up converter keeps the average output voltage VSYS higher than DC input voltage VIN, and its circuit diagram is shown in Figure 15-a. Figure 15-b shows an operational waveform in case inductor current is steady-state. Since in steadystate, the integral of the inductor voltage over one time period to zero, this can be expressed by the following formula:
(VIN x t ON ) + ((VIN - VSYS ) x tOFF ) = 0
From the above formula, a redefined formula is as follows after dividing by cycle Ts:
VSYS T 1 = S= VIN t OFF 1 - D VSYS = 1 x VIN [V ] 1- D
Assuming a lossless circuit, input and output power are the same (Pin=Po) and the above formula can be redefined as follows:
VIN I IN = VSYS I O
This can be expressed as follows using input/output current and duty ratio:
IO = (1 - D) I IN
In the boundary condition of continuous mode and discontinuous mode, the inductor's average current is defined as follows:
1 iLB = iL, peak 2 1 VIN = TON 2L TV = S SYS D(1 - D)2 2L
From the above formula, since inductor current and input current are the same (iIN=iL), the average output current at the edge of continuous conduction mode can be redefined as below:
I OB =
TS x VSYS D(1 - D) 2 2L
In a practical synchronous step-up converter, the parasitic elements are due to the loss associated with the inductor, the capacitor and the switches; however, in this formula we assume that all components are at ideal conditions.In the continuous mode, as the output current and peak-peak voltage ripple are considered to be constant, this formula can be redefined as below:
VSYS =
Q I O DTS VSYS DTS = = C C RC
VSYS DTS = VSYS RC
Where,
R=
VSYS [] IO
21
FAN8048
In Figure 16, when control voltage VX is always higher than VY and triangular waveform voltage VPCT, Switch pairs C and D will alternately switching and their circuit is designed to operate as a step-up converter, whose output voltage is always higher than input voltage. Figure 15 shows the operational waveform at the output terminal of each switching device when it acts as a step-up converter. In this operations section, Switch A is always turned-on and switch B is always turned-off. Also, to limit the maximum output voltage in this mode, the maximum duty ratio is limited to about 75%.
A
D
VD
VIN
VB
B
(a)
VC
VSYS C
R
VL
0
A
(VIN)
VSYS
t
B
(VIN-VSYS)
iL
0
Ton
Toff
t
Ts
(b)
Figure 15. Synchronous Step-up Converter
VX PCT VY
VA VB
High
Low
VC
VD
Figure 16. Output switch operational waveforms in Boost (Step-up) converter mode
22
FAN8048
3.10.1 Effect of Parasitic Elements in Step-up Converter
In a practical synchronous step-up converter, the parasitic elements are due to the loss associated with the inductor, the capacitor and the switches; however. Figure 17 qualitatively show the effect of these parasitics on the voltage transfer ratio. Unlike the ideal characteristic, in paractice VSYS/VIN declines as the duty ratio approaches unity. Because of very poor switch utilization at high values of duty ratio, the curves in this range are show as dotted.
VSYS VIN 1 1- D
Ideal
Due to parasitic elements
D 0 1
Figure 17. Effect of parasitic elements on voltage conversion ratio
23
FAN8048
3.11 Component of Error Amplifier Compensation Network
In this chapter, we would like discuss the method of converter error amplifier design to control voltage mode PWM. In general, a negative feedback control circuit composed of error amplifier using an operational amplifier and comparator is often used to stabilize output voltage in switching mode converters. Controller design standards and methods for a stable system are as follows: (1) To reduce regulation error of the output voltage, the loop gain crossover frequency, fC, should be as high as possible. (2) To obtain stable phase margin, let the slope gain at 0dB be -20dB/dec. That is, have the gain phase at 0dB close to -90. (3) Set the loop gain crossover frequency, fC be set to 1/5 ~ 1/10 of the switching frequency fS. But in boost converter, due to the RHP zero, fRHPZ, the loop gain frequency, fC, must be designed well below the RHP zero because the boost converter have a right half plane (RHP) zero. ( fC =fRHPZ /10) (4) Set compensation pole, fP1 to cancel the ESR zero fFILTER_ZERO. (fP1= fFILTER_ZERO) (5) Place a high-frequency compensator pole, fP2 to get the maximum attenuation of the switching ripple and high frequency noise the minimum phase lag at fC. (6) Place a two compensator zeroes, fZ1 and fZ2 below fC. Place the fz1 below the power stage natural frequency, fFILTER_POLE to avoid a conditional stability. When setting these two zeroes (fz1 and fz2), converter performance and stability margin should be considered. (7) Select the compensator parameters. (R's and C's ) To meet the design standards mentioned above, Figure 18 shows circuits and the characteristics of a typical compensator, which has a controller structure with two zeroes (fz1 and fz2) and poles (fp1 and fp2). First of all to design an error amplifier, natural frequency of system, fFILTER_POLE and ESR zero using an equivalent series resistance of the output capacitor can be obtained by the following formula. Double poles by the output filter are obtained from the following formula:
f FILTER _ POLE =
Where, Co is the output capacitor.
1 [ Hz ] 2 LC O
The ESR zero by the output capacitor, CO and equivalent series resistance of the output capacitor, RESR can be obtained by the following formula.
f FILTER _ ZERO =
1 [ Hz ] 2 x RESR x CO
where, RESR is the equivalent series resistance of output filter capacitor.
VSYS
C3 C2 R3 C1 R2
Gain
Av2
-20dB/dec = -2slop 20dB/dec = +2slop
Phase
-20dB/dec = -2slop
R1
10 11
Vc
0.9V
Av1 +90o
R4
Note
C1>>C3 R1>>R3
Error Amp
0o -90o
f1 f2 f3 f4
Figure 18. Error Amplifier Compensation Circuit
24
FAN8048
A troublesome feature in boost converter mode is the right-half plan (RHP) zero, and is given by:
f RHPZ =
VIN [ Hz ] 2 x I O x L
2
.Most applications demand an improved transient response to allow a smaller output filter capacitor, and to achieve a higher bandwidth, type 3 compensation is required. In Figure 18, pole and zero of the error amplifier are expressed as follows:
1 [ Hz ] 2 x R1x (C1 + C 3) 1 f Z1 = [ Hz ] 2 x R 2 x C1 1 fZ 2 = [ Hz ] 2 x C 2( R1 + R3) 1 f P1 = [ Hz ] 2 x R3 x C 2 1 f P2 = [ Hz ] C1x C 3 2 x R 2 x C1 + C 3 fI =
And because it has C1 >> C3 and R1 >> R3 in general, it can be simplified as below:
1 [ Hz ] 2 x R1x C1 1 f Z1 = [ Hz ] 2 x R 2 x C1 1 fZ 2 = [ Hz ] 2 x R1x C 2 1 f P1 = [ Hz ] 2 x R3 x C 2 1 f P2 = [ Hz ] 2 x R 2 x C 3 fI =
25
FAN8048
3-12. Considerations of Input and Output Capacitors in DC-DC converter Input Capacitors
The input capacitor is necessary to minimize the peak current drawn from the battery. Typically a several ten times uF tantalum capacitor is recommending. Low equivalent series resistance (ESR) capacitors will help to minimize battery voltage ripple.
Output Capacitors
Low ESR capacitors should be used at the output of the DC-DC converter to minimize output ripple. The high frequency switching speeds and fast changes in the output capacitor current, mean that the equivalent impedance of the capacitor can contribute greatly to the output ripple. In order to minimize these effects choose an output capacitor with less than 10nH of equivalent series inductance (ESL) and less than 100mW of equivalent series resistance (ESR). Typically these characteristics are met with ceramic capacitor, but may also be met with certain types of tantalum capacitor. For a step change of load, the output filter inductor in Figure 19 acts as a source of constant current during in this load transient, and the change in load current as a transient is supplied by the filter capacitor. Hence, following a load transient,
VSYS = - ESR x I SYS
3-13. Layout and Ground Considerations
High frequency switching and large peak currents means PCB design for DC-DC converters requires careful consideration. A general rule is to place the DC-DC converter circuitry well away from any sensitive RF or analog components. The layout of the DC-DC converters and its external components are also based on some simple rules to minimize EMI and output voltage ripple.
Layout
1. Place all power components, FAN8048, inductor, input capacitor and output capacitor as close together as possible. 2. Keep the output capacitor as close the FAN8048 as possible with very short traces to the VSYS and GND pins. 3. Keep the external feedback loop network as close the FAN8048 as possible with very short traces, but away from the four channels output as far as possible.
Grounding
1. Use a star grounding system with separate traces for the power ground and the low power signals such as ON/OFF and MUTE. The star should radiate from where the power supply enters the PCB. 2. On the multilayer boards use components side copper for grounding around the FAN8048 and connect back to a quiet ground plane using vias.
iL
iSYS
L
ESR VSYS C R=Load
Output Filter
Figure 19. ESR in the output capacitor
26
FAN8048
4. Series Voltage Regulator and Battery Charger Function
As shown in Figure 20, if the external adaptor supplies high voltage (in general, adaptor voltage used for portable devices is above 4.5V), the series voltage regulator is internally designed to be 4V so as to be suitable for circuit operation; and when necessary, it has the function of battery charging using an external adaptor.
4.1 Non-charging mode (Series Voltage Regulator Function)
When battery-charging mode is unnecessary, CHGSW (pin27) input may be LOW. On this occasion, the output voltage VREG (Voltage on pin18) of the series voltage regulator is internally designed to be 4.0V. When DCIN(pin24) is not supplied (when VIN is connected from the batteries), this circuit is need diode(D1) for prevent the VIN (Volatege on pin18) leakage current can not flow in to the IC. The related formula for this is expressed as follows:
V REG = ((1 +
R1 ) x 0.5) - V Q1, SAT = 4[V ] R2
4.2 Charging mode (Battery Charger function)
To charge the battery using an external adaptor, CHGSW ( pin27) input should be HIGH. In charging mode, internal transistor Q1 and external transistor Q3 are turned-on to connect the battery with the external adaptor. On this occasion, charging current, iCHG can be determined by current detection resistance Rs, and charging current is obtained by the following formula:
I CHG =
0.5 [ A] RS
DCIN
24
REG 0.5V
23
Q2 VIN D1
18
DC-DC Converter
R1
DCIN
R2
Q1
iCHG
26
CHGSW 27
Charge_ON
Q3 CHGCON CHGSEN
25
RS
Figure 20. Block Diagram of Regulator and Battery charger
Adaptor
27
FAN8048
5. Precaution
1. Attach a de-coupling capacitor between power supply pins and ground. 2. Check that the following items will not result while this IC is in use, or otherwise the IC will be broken or burned with smoke generated. -. Short-circuiting between output pins -. Short-circuiting between output and ground pins -. Short-circuiting between output and power supply pins -. Reverse insertion of IC The following pins are all output pins. VG(pin1), RST(pin2), EA1O(pin10), EA2O(pin12), VSYS2(pin14), USW2(pin15), DSW2(pin17), DSW1(pin19), USW1(pin21), VSYS1(pin22), REG(pin23), CHGCON(pin26), CH4-(pin38), CH4+(pin39), CH3-(pin40), CH3+(pin41), CH2-(pin43), CH2+(pin44), CH1-(pin45) and CH1+(pin46) The following pins are all ground pins. SGND(pin6), PGND(pin16), PGND(pin20), DGND(pin28), PGND(pin37) and PGND(pin47) The following pins are all power supply pins. VIN(pin18), DCIN(pin24) and PVCC(pin42)
Note) This document provides reference information on the use of this IC, which does not, however, guarantee the proper operation of any applications employing this IC. Constantly or values provided in this document are reference values and not guaranteed values.
28
FAN8048
Typical Performance Characteristics
Temperature vs Ivin
Temperature vs Ivg
1.6 1.4 1.2
3 2.5 2 Ivin[mA]
Ivg[mA]
1 0.8 0.6 0.4
1.5 1 0.5 0 -35
0.2 0 -35 -15 5 25 Temperature [] 45 65 85
-15
5
25 Temperature []
45
65
85
Temperature vs Idcin
0.8
Temperature vs Vvg
9 8
0.6
Idcin [mA]
Vvg [V]
0.4
7 6 5 -35
0.2
0 -35
-15
5
25
45
65
85
-15
5
25
45
65
85
Temperature []
Temperature [ ]
Tem perature vs fosc
150
Temperature vs flg
80 75 fosc [KHz] 70 65 60 55 50 -35 -15 5 25 Tem perature[ ] 45 65 85
flg [KHz] 130
110
90
70
50 -35
-15
5
25 Temperature []
45
65
85
29
FAN8048
Typical Performance Characteristics
Temperature vs Vup
2.85 2.8
Vdown [V] 2.85 2.8 2.75 2.7 2.65 2.6 2.55 -35 Vdown1 Vdown2 Temperature vs Vdown
2.75 Vup[V] 2.7 2.65 2.6 2.55 -35 Vup1 Vup2
-15
5
25 Temperature [ ]
45
65
85
-15
5
25 Temperature []
45
65
85
VIN vs VSYS
2.9
4.3 4.2
DCIN vs VIN(Regulator Output)
2.8 VSYS [V]
VIN(V)
VSYS1 VSYS2
4.1 4 3.9
2.7
2.6
3.8
2.5 1.8
2.1
2.4
2.7
3
3.3
3.6
3.9
4.2
4.5
3.7 4.5
5.5
6.5
7.5
DCIN(V)
8.5
9.5
VIN [V]
30
FAN8048
Typical Performance Characteristics (Continued)
Output Switches Rdson of DC-DC Converter1 0.60 Rdsw_Upper 0.50 0.40 Rdson[] 0.30 0.20 0.10 0.00 0 50 100 150 200 250 300 350 400 450 I_load[mA] Rdsw_Low Rusw_Upper Rusw_Low
Output Switches Rdson of DC-DC Converter2 0.60 0.50 Rdson[] 0.40 0.30 0.20 0.10 0.00 0 50 100 150 200 250 300 350 400 450 I_load[mA]
Rdsw_Upper Rdsw_Low Rusw_Upper Rusw_Low
Output Switches Rdson of Channel 1
1.00 0.90 0.80 Rdson[] 0.60 0.50 0.40 0.30 0.20 0 50 100 150 200 250 300 350 400 450 I_load[mA]
Rdson[] 1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0 50
Output Switches Rdson of Channel 2
0.70
Ron1+_hi Ron1+_lo Ron1-_hi Ron1-_lo
Ron2+_hi Ron2+_lo Ron2-_hi Ron2-_lo
100
150
200
250
300
350
400
450
I_load[mA]
Output Switches Rdson of Channel 3
1.00
Output Switches Rdson of Channel 4
1.00 0.90 0.80 Rdson[] 0.60 0.50 0.40 0.30 0.20 0 50 100 150 200 250 300 350 400 450 I_load[mA]
Ron3+_hi Ron3+_lo Ron3-_hi Ron3-_lo
0.90 0.80 Rdson[] 0.70 0.60 0.50 0.40 0.30 0.20 0 50 100 150 200 250 I_load[mA] 300 350 400 450
Ron4+_hi Ron4+_lo Ron4-_hi Ron4-_lo
0.70
31
FAN8048
Typical Application Circuits
VBATT
L1
LG
D1
48 1
VG
47
PGND
46
CH1+
45
CH1-
44
CH2+
43
CH2-
42
PVCC
41
CH3+
40
CH3-
39
CH4+
38
CH4-
37
PGND
36 35 34 33 32
CH4F
C1
2 3 4 5
C2
CH4R
RST
OFF
CH3F
ON
CH3R
SPRT
CH2F
6 7
C3
SGND
PCT
FAN8048
31 30 29
CH2R
CH1
8
MUTE
CLK
9
C4
SOFT
28 27 26
DGND
10
C5 C6 R1
EA1O
CHGSW
R9
11 12
EA1-
CHGCON
Q2
EA2O EAI2VSYS2 USW2 PGND DSW2 VIN DSW1 PGND USW1 VSYS1 REG DCIN
25 14
R3 C9 C11 R4
CHGSEN
R8
13
15
16
17
18
19
20
21
22
R5
23
R7
24
C7
R2
Q1
L2
L3
R6 D2
C8
VSYS2
VBATT
C10
VSYS1
DCIN DCGND
SYSTEM ON SYSTEM OFF RESET CLOCK
Servo Amp & Controller
Tracking F R Focus F R F Sled R Spindle MUTE CHGSW
32
Battery
FAN8048
Package Dimensions
48-LQFP-0707
33
FAN8048
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 1/8/04 0.0m 001 Stock#DSxxxxxxxx 2004 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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